Headquartered in Shanghai

Layout and physical design services for advanced-node IC programs

DUSTERATECH is an IC Design Service company headquartered in Shanghai. We support chip design companies, system vendors and high-end IC development teams with analog layout, physical design, ASIC turnkey coordination and wafer shuttle services.

Process350nm-22nm CMOS
16nm-5nm FinFET
ApplicationsWiFi / Bluetooth / IoT
Short-range RF
FocusLayout / Physical Design
ASIC Turnkey / Shuttle
About

An IC design service team grounded in layout and physical design capability.

DUSTERATECH was founded in 2022 and is headquartered in Shanghai. The team focuses on IC layout design services and professional consulting.

Our capability spans 350nm-22nm CMOS nodes and 16nm-5nm FinFET advanced-node physical design, with emphasis on high-end programs at 28nm and below.

We focus on short-range RF technologies such as WiFi and Bluetooth, serving consumer electronics and IoT applications.

Services

Four core services built around tapeout-ready delivery.

DUSTERATECH organizes service scope around engineering delivery, from layout implementation and physical design to ASIC coordination and wafer shuttle interfaces.

01 / Analog Layout

IC Analog Layout Design

Professional layout support for RF, analog and mixed-signal blocks where matching, parasitics, noise and reliability matter.

  • Device placement, matching, isolation and parasitic control
  • Critical routing, metal hierarchy and power integrity
  • Front-end advice on device selection and circuit floorplanning
02 / Physical Design

IC Physical Design

Advanced-node physical implementation support for high-end IC programs at 28nm and below.

  • Floorplan, placement, CTS and routing coordination
  • Timing, power, area and congestion closure
  • Physical design capability across 16nm-5nm FinFET nodes
03 / ASIC Turnkey

ASIC Custom / Turnkey

Program-level support for ASIC customization, design coordination, manufacturing interface and delivery management.

  • Requirement breakdown and process-node evaluation
  • Multi-discipline design resource coordination
  • Reduced complexity from specification to tapeout
04 / Wafer Shuttle

Wafer Shuttle Services

Support for MPW and shuttle projects, including manufacturing interface, tapeout package checks and engineering follow-up.

  • MPW / shuttle planning and coordination
  • Design data readiness and foundry interface support
  • Sample-stage issue tracking and engineering closure
350-22nm CMOS experience across mature and mainstream production nodes.
16-5nm FinFET physical design capability for advanced-node programs.
28nm↓Focused support for high-end chip development at 28nm and below.
RF/IoTWiFi, Bluetooth, short-range RF, consumer electronics and IoT focus.
Delivery Flow

A clear process reduces uncertainty in IC development.

Each stage aligns constraints, risks and deliverables before the project moves forward.

IN_01

Requirement Review

Chip type, process node, scope, existing data and confidentiality requirements.

PLAN_02

Technical Plan

Constraints, risks, resources and staged deliverables.

EXEC_03

Execution

Layout, physical design, ASIC coordination or tapeout interface work.

CHECK_04

Closure

Rule, timing, reliability, parasitic and delivery-quality closure.

OUT_05

Delivery Support

Engineering data delivery, tapeout support and follow-up communication.

Contact

Start with a technical evaluation and turn requirements into an executable IC design plan.

Please include chip type, process node, module scope, project phase, target tapeout time and available design materials.

COMPANY

Company

DUSTERATECH